1. Field of the Invention
The invention relates to a voltage level shifter, and in particular relates to a voltage level shifter avoiding current leakage.
2. Description of the Prior Art
Referring to FIG. 1, a schematic diagram of conventional voltage level shifter 100 is shown. Conventional voltage level shifter 100 includes: a inverting module 110, a latch circuit 140, inverting circuits 160 and 180 and an output circuit 195. Inverting module 110 includes NMOS transistors 111 and 112 and a PMOS transistor 113. NMOS transistor 111 has a drain for receiving an input signal Vin, a gate for receiving a voltage source VDD and a source coupled to ground voltage. NMOS transistor 112 has a drain coupled to node 121, a gate for receiving the input signal Vin and a source coupled to ground voltage. PMOS transistor 113 has a drain coupled to node 121, a gate for receiving the input signal Vin and a source for receiving the voltage source VDD.
Inverting circuit 160 includes NMOS transistors 161, 163, 164 and 165 and a PMOS transistor 162. NMOS transistor 161 has a drain coupled to the gate of NMOS transistor 163, a gate for receiving the input signal Vin and a source coupled to ground voltage. NMOS transistor 163 has a drain coupled to NMOS transistor 164, a gate coupled to NMOS transistor 161 and a source coupled to ground voltage. NMOS transistor 164 has a drain coupled to NMOS transistor 165, a gate for receiving the voltage source VDD and a source coupled to NMOS transistor 164. NMOS transistor 165 has a drain coupled to node N1, a gate for receiving a voltage source VBAT and a source coupled to NMOS transistor 164. PMOS transistor 162 has a drain coupled to NMOS transistor 161, a gate for receiving the input signal Vin and a source for receive the voltage source VDD. Voltage source VDD is generated from the voltage source VBAT by voltage dividing.
Inverting circuit 180 includes NMOS transistors 181, 183, 184 and 185 and a PMOS transistor 182. NMOS transistor 181 has a drain coupled to a gate of NMOS transistor 183, a gate coupled to node 121 and a source coupled to ground voltage. NMOS transistor 183 has a drain coupled to NMOS transistor 184, a gate coupled to NMOS transistor 181 and a source coupled to ground voltage. NMOS transistor 184 has a drain coupled to NMOS transistor 185, a gate coupled to the voltage source VDD and a source coupled to NMOS transistor 183. NMOS transistor 185 has a drain coupled to node N2, a gate coupled to the voltage source VBAT and a source coupled to NMOS transistor 184. PMOS transistor 182 has a drain coupled to NMOS transistor 181, a gate coupled to node 121 and a source for receiving the voltage source VDD.
Latch circuit 140 includes PMOS transistors 141 and 142. PMOS transistor 141 has a drain coupled to node N1, a gate coupled to node N2 and a source coupled to the voltage source VBAT. PMOS transistor 142 has a drain coupled to node N2, a gate coupled to node N1 and a source coupled to the voltage source VBAT. Output circuit 195 includes inverters 196 and 197. Inverter 196 is coupled between the voltage sources VBAT and VSS and has an input terminal coupled to node N1 and an output terminal coupled to inverter 197. Inverter 197 is also coupled between the voltage source VBAT and ground voltage and has an input terminal coupled to inverter 196 and an output terminal for outputting an output signal Vout.
Conventional voltage level shifter 100 can be used in logic circuits of a computer system. While the computer system does not provide voltage source VDD or voltage source VDD is low, inverters 196 and 197 have leakage current due to node N1 of voltage level shifter 100 is floating connected.